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AMD~
AMD5/36
Processor
Technical
Reference
Manual
1 8524B/O-Marl
996
5.2.43
Summary
PWT
(Page
Writethrough)
Output
The
processor
drives
PWT
to
indicate
the
operating
system's
specification
of
writeback
or
writethrough
state
for
the
entire
current
page.
PWT,
together
with
WBIWT,
specifies
the
data-
cache
MESI
state
of
cacheable
read
misses
and
write
hits.
Driven
and
floated
The
processor
drives
PWT
from
the
clock
in
which
ADS
is
asserted
until
the
last
expected
BRDY
of
the
bus
cycle.
Details
5-106
PWT
is
driven
during
memory
cycles
(including
cache
writethroughs
and
writebacks),
and
locked
cycles
in
the
nor-
mal
operating
modes
(Real,
Protected,
and
Virtual-8086),
and
in
SMM,
and
when
PRDY
is
asserted.
If
AHOLD is
asserted,
PWT
is
driven
only
to
complete
a
bus
cycle
that
had
been
initi-
ated
before
AHOLD
was
asserted.
PWT
is
not
driven
during
special
bus
cycles
or
interrupt
acknowledge
operations;
or
in
the
Shutdown,
Halt
or
Stop
Grant
states,
except
for
write
backs
due
to
inquire
cycles;
and
PWT
is
never
driven
during
the
Stop
Clock
state,
or
while
BUFF,
HLDA,
RESET,
or
INIT
is
asserted.
The
processor
floats
PWT
one
clock
after
system
logic
asserts
BUFF
and
in
the
same
clock
that
the
processor
asserts
HLDA.
As
Table
5-14 shows,
lines
in
the
modified
or
exclusive
MESI
state
are
said
to
be
in
the
writeback
state,
which
corresponds
to
PWT
=
O.
Lines
in
the
shared
MESI
state
are
said
to
be
in
the
writethrough
state,
which
corresponds
to
PWT
=
1.
TABLE
5-14.
PWT,
WritebackfWritethrough,
and
MESI
MESIState
Writeback/Writethrough State
PWT
State
modified writeback 0
exclusive writeback 0
shared write through 1
invalid invalid
-
System
logic
can
use
PWT
output,
along
with
its
WBIWT
input,
to
determine
how
the
processor
will
control
internal
caching.
Tables
5-17
and
5-18
on
page
5-136
show
how
the
state
of
PWT
and
WBIWT
determine
the
MESI
state
of
a
line
in
the
data
cache
after
a
cache-line
fill
or
write
back.
If
WBIWT
is
Low
or
PWT
is
High
during
a
read
miss
or
a
write
hit
to
a shared
line,
Bus
Interface

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