AMD AMD5K86 - Machine-Check Exceptions

AMD~
18524B/0- Marl 996 AMD51J6 Processor Technical Reference Manual
TABLE 3-1. Control Register 4 (CR4) Fields
Bit Mnemonic
Description
Function
Enables retention of designated entries in the
4-Kbyte TLB or 4-Mbyte TLB during invalida-
7
GPE
Global Page
tions.
Extension
1 = enabled, 0 = disabled.
See Section 3.1.3 on page 3-9 for details.
Enables machine-check exceptions.
6 MCE
Machine-Check
1 = enabled, 0 = disabled.
Enable
See Section 3.1.1 on page 3-4 for details.
Enables 4-Mbyte pages.
4
PSE
Page Size
1 = enabled, 0 = disabled.
Extension
See Section 3.1.2 on page 3-5 for details.
Enables I/O breakpoints in the DR7-DRO regis-
Debugging
ters.
3
DE
Extensions 1 = enabled, 0 = disabled.
See Section 7.5 on page 7-16 for details.
Selects privileged (CPL=O) or non-privileged
(CPL>O) use of the RDTSC instruction, which
2 TSD
Time Stamp
reads the Time Stamp Counter (TSC).
Disable
1 = CPL must be 0, 0 =any CPL.
See Section 3.2.3 on page 3-27 for details.
Enables hardware support for interrupt virtu-
Protected Virtual
alization in Protected mode.
1 PVI
Interrupts 1 = enabled, 0 = disabled.
See Section 3.1.5 on page 3-24 for details.
Enables hardware support for interrupt virtu-
Virtual-8086
alization in Virtual-8086 mode.
0
VME
Mode Extensions 1 = enabled, 0 = disabled.
See Section 3.1.4 on page 3-12 for details.
Control Register 4 (CR4) Extensions
3-3