AMD AMD5K86 - HOLD (Bus-Hold Request)

18524B/O-Mar1996
Signal Descripuons
AMD~
AMD5~6 Processor Technical Reference Manual
Unlike BUFF, the assertion of HOLD does not abort an in-
progress cycle. If the processor is not driving a bus cycle when
HOLD is asserted, the bus master asserting or causing the
assertion of HOLD can begin driving its first bus cycle in the
clock after HLDA is asserted, which occurs two clocks after
HOLD is asserted. The processor supports only one in-progress
bus cycle. Unlike the Pentium processor, no pending bus cycles
are held in write buffers between the data cache and the bus
interface on the AMD5
K
86 processor.
The processor can assert ADS in the clock after HOLD is
asserted (but before asserting HLDA) and drive a bus cycle
before acknowledging HOLD with HLDA. System logic may
assert EADS for an inquire cycle as early as one clock after the
processor asserts HLDA.
The processor continues driving HLDA until two clocks after
HOLD is negated, at which time the processor may again drive
its own cycles with ADS in the next clock after it negates
HLDA. The processor responds to inquire cycles while HLDA
is asserted and will assert HIT and IIITM in response to such
cycles. If IIITM is asserted, the writeback is performed imme-
diately after HLDA is negated. Multiple inquire cycles are not
permitted to hit modified lines. The processor implements this
restriction by ignoring EAUS while IIITM is asserted; when
IIITM is asserted, it is held asserted until one clock after the
last BRDY of the writeback.
For a list of signals recognized while HLDA is asserted, see
Table 5-2 on page 5-9. See the description of HOLD on page 5-
78 for additional details about the HOLD/HLDA protocol.
5-77