AMD AMD5K86 - FIGURE 5-25. Branch-Trace Message Cycle

AMD~
AMD5f1J6 Processor Technical Reference Manual 18524BjO-Mar1996
Branch-Trace
Message Cycles
Figure 5-25 shows the two branch-trace message special bus
cycles that the processor generates for each taken branch
when branch tracing is enabled as described in Section 7.6 on
page 7-17. System logic can accumulate the address and data
bus values for debugging or profiling.
The processor drives these special bus cycles immediately
after each taken-branch instruction is executed. Both special
bus cycles have a BE7-BEO = DFh, and system logic must
respond by asserting BRDY to each of the cycles. The first
cycle identifies the branch source, and the second identifies
the branch target, as shown in Table 5-24.
TABLE 5-24. Branch-Trace Message Special Bus Cycle Fields
Signals First Special Bus Cycle Second Special Bus Cycle
A31
0= first special bus cycle (source)
1 =
second special bus cycle (target)
Operating Mode of Target:
11 = Virtual-8086 Mode
A30-A29 not valid
10 = Protected Mode
01 = Not valid
00 = Real Mode
Default Operand Size of Target Segment:
A28
not valid
1 = 32-Bit
0= 16-Bit
A27-A20
0
0
A19-A4
Code segment (CS) selector of Code segment (CS) selector of branch
branch source target
A3
0
0
D31-AO
EIP of branch source. EIP of branch target.
5-188
Bus Interface