AMD AMD5K86 - Branch Tracing

18524B/O-Mar1996
7.5.3
AMD~
AMD5J!36 Processor Technical Reference Manual
Enabled breakpoints slow the processor somewhat. When a
data breakpoint is enabled, the processor disables its dual-
issue load!store operations and performs only single-issue load!
store operations. When an instruction breakpoint is enabled,
instruction issue is completely serialized.
Debug Compatibility with Pentium Processor
The differences in debug functions between the AMD5
K
86 and
Pentium processors are described in Section A.7 on page A-15.
7.6 Branch Tracing
Branch Tracing
Branch tracing is enabled by writing bits 3-1 with 00lb and set-
ting bit 5 to 1 in the Hardware Configuration Register
(HWCR), as described in Section 7.1 on page 7-3. When thus
enabled, the processor drives two branch-trace message spe-
cial bus cycles immediately after each taken branch instruc-
tion is executed. Both special bus cycles have a BID-BED
encoding of DFh (1101_1111b). The first special bus cycle iden-
tifies the branch source, the second identifies the branch tar-
get. The contents of the address and data bus during these
special bus cycles are shown in Table 7-4.
The branch-trace message special bus cycles are different for
the AMD5
K
86 and Pentium processors, although their BID-
BED encodings are the same.
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