AMD AMD5K86 - Bus Cycle Order of Misaligned Memory and I;O Cycles; Selectable Drive Strengths on Output Driver

AMD~
AMD5~6 Processor Technical Reference Manual
18524B/O-Mar1996
A.2.]
A.2.4
A.2.S
A-6
same as the locked misaligned and locked aligned
CMPXCHG8B operations, respectively, described above.
On an unlocked and cacheable CMPXCHG8B operation, the
AMD5
K
86 and Pentium processors behave the same.
Bus Cyde Order of Misaligned Memory and 1/0 Cydes
The AMD5
K
86 processor performs split (misaligned) memory
read, memory write, and 110 read cycles in the reverse order of
the Pentium processor. Split 110 write cycles occur in the same
order on both processors.
Halt Cyde after FLUSH
When halted, the AMD5
K
86 processor reruns a Halt special
cycle after the Flush Acknowledge special cycle following a
cache flush operation. The Pentium processor does not rerun a
Halt special cycle.
Selectable Drive Strengths on Output Driver
The AMD5
K
86 processor supports selectable drive strengths on
the following output pins:
• A20-A3
• WIR
• ADS
• HITlVI
This is the same set of output pins that have selectable drive
strengths on the Pentium processor. However, the Pentium
processor supports three drive strengths on these pins while
the AMD5
K
86 processor supports two.