AMD AMD5K86 - FERR (Floating-Point Error)

AMD~
AMD5xB6 Processor Technical Reference Manual
18524BjO-Mar1996
5-64
latches any edge·triggered interrupt that may not be recog·
nized while EWBE is negated (FLUSH, BMJ, NMI) and recog·
nizes them in priority order when EWBE is asserted.
If system logic implements memory·mapped 110 as non·cache·
able memory (the standard method), EWBE on the AMD5
K
86
processor has the same effect on writes to memory·mapped 110
as does EWBE on the Pentium processor-neither processor
reorders reads ahead of writes.
For more details on the function of EWBE, see the following
sections:
• BRDY-Page 5·42.
• HITlVI-Page 5·74.
• BMJ-Page 5·117.
• SMIACT-Page 5·122.
• STPCLK-Page 5·123.
Bus Interface