AMD AMD5K86 - Page 184

AMD~
18524BjO- Marl 996 AMD5J!36 Processor Technical Reference Manual
5.2.22
FED (Floating-Point Error)
Output
Summary
Driven
Details
Signal Descriptions
The processor asserts FERR to report floating-point errors in a
manner compatible with floating-point software written for
287 and 387 coprocessors. The IGNNE input controls the
behavior of FERR.
The processor drives FERR every clock during memory cycles
(including cache writethroughs and writebacks), cache hits of
all types, 110 cycles, and lbcked cycles in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM. FERR
is not driven during the Shutdown, Halt, Stop Grant, or Stop
Clock states, or while RESET, INIT, or PRDY is asserted.
FERR and IGNNE support backward compatibility with float-
ing-point software designed for 287 and 387 coprocessors on
PC systems running DOS. Contemporary floating-point soft-
ware typically observes these same conventions and requires
these signals.
If software has set the numeric error (NE) bit in CRO to 1, the
processor reports unmasked floating-point exception condi-
tions in the way specified for 287 and 387 coprocessors-the
processor asserts FERR to report the error externally while
internally the processor generates a numeric error exception
(10h) while executing the next WAIT instruction or at the
beginning of the next computational floating-point instruction.
The IGNNE input plays no part in error reporting if the NE bit
in CRO is set to 1.
If software has cleared the numeric error (NE) bit in CRO to 0,
unmasked floating-point exception reporting depends on the
state of the IGNNE input, as follows:
• If the IGNNE input is negated, the processor reports
unmasked floating-point exception conditions in a way that
is compatible with IBM-compatible PC/AT systems-the
processor asserts FERR to report the error externally to a
busy latch (FERR is analogous to the ERROR output on 287
and 387 coprocessors). The external busy latch generates
IRQ13 if FERR is asserted, and the service routine for
IRQ13 can then assert IGNNE to permit continued process-
ing of floating-point instructions.
5-65