AMD AMD5K86 - FIGURE 5-21. Shutdown Cycle

AMD~
AMD5J!J6 Processor Technical Reference Manual 18524B/O-Mar1996
Basic Special Bus
Cycle
ClK
~
A31-A3
AlJ5
BEl-BED
BRDY
DfC
EWBE
MjIlJ
W(R
ClK
,
Figure 5-20 shows a basic special bus cycle, which is defined
during ADS by DiC = 0, M/IO = 0, and WIR = 1 and differenti-
ated by BE7-BEO and A31-A3. In this example, BE7-BEO
= FBh and A31-A3 = 0, so it is the special cycle the processor
generates after executing a HLT instruction. System logic must
respond with BRDY.
All special bus cycles serialize the pipeline. EWBE is not
checked prior to running special bus cycles (all of which have
WIR = 1), so EWBE has no effect on any special bus cycles.
\
(
\ \ \ 1
X
\ I
X
\
I
\
\
Y
\
\
\
r-
FIGURE 5-20. Basic Special Bus Cyde (Halt Cyde)
5-182 Bus Interface