AMD AMD5K86 - STPCLK (Stop Clock)

AMD~
AMD5~6 Processor Technical Reference Manual
18524BjO-Mar1996
5.2.48
Summaty
Driven
Details
5-122
SMIACT (System Management Interrupt Active)
Output
The processor acknowledges the assertion of sm with the
assertion of SMIACT. The acknowledgment signifies the pro-
cessor's readiness to enter System Management Mode (SMM)
and begin executing the service routine for that interrupt
mode.
The processor drives SMIACT from after the later of (a) the
last expected BRDY of any in-progress bus cycle, or (b) the
assertion of EWBE with or following the last expected BRDY,
until the return from the SMM interrupt handler via the RSM
instruction.
SMIACT is driven during memory cycles (including cache
writethroughs and writebacks), cache accesses, I/O cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; in the Shutdown, Halt, or Stop
Grant states; or while AHOLD, BUFF, HLDA, or PRDY is
asserted. SMIACT is not driven in the Stop Clock state, or
while RESET is asserted.
The memory controller normally uses the assertion of SMIACT
to enable SMM memory, so that the first memory access in
SMM is to the base of the state-save area in the SMM memory
space.
The processor remains in SMM, continuing to assert SMIACT,
until it executes the RSM instruction. For more information
regarding SMM, see the description of SMI on page 5-117, Sec-
tion 6.1.4 on page 6-5, and Section 6.3 on page 6-23.
Bus Interface