AMD AMD5K86 - STPCLK (Stop Clock)

AMD~
18524B/O-Mar1996 AMD5,!36 Processor Technical Reference Manual
5.2.49 STPCLK (Stop Clock)
Summary
Sampled and
Acknowledged
Details
Signal Descriptions
Input
The assertion of STPCLK causes the processor to complete any
in-progress bus cycle and enter the Stop Grant state (proces-
sor's internal clock stopped), from which it can subsequently
transition to the Stop Clock state (bus clock stopped). These
low-power clock states can be entered from the normal operat-
ing modes, system management mode (SMM), or the Halt state.
The processor samples STPCLK every clock and recognizes it
at the next instruction boundary. STPCLK is a level-sensitive
interrupt with an internal pullup resistor. The signal must be
held asserted until recognized. When STPCLK is recognized
and EWBE is asserted, the processor acknowledges it by driv-
ing a Stop Grant special bus cycle, waits for BRUY, then stops
its internal clock and floats D63-DO and DP7-DPO.
STPCLK is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, 110 cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; or in the Shutdown, Halt, or
Stop Grant states. STPCLK is not sampled in the Stop Clock
state, or while RESET, INIT, or PRDY is asserted. STPCLK is
not meaningful if it is asserted while AHOLD, BUFF, or HLDA
is asserted, because the processor cannot drive the Stop Grant
special bus cycle.
STPCLK is the lowest-priority external interrupt. For details
on its relationship to other interrupts and exceptions, see Sec-
tion 5.1.3 on page 5-14 and Table 5-3 on page 5-17.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
In typical PC systems that implement power control, the STF-
CLK, CLK, and SlVIT signals are driven by external power man-
agement logic. This logic monitors activity on the address and
cycle definition signals. In a typical case, the power manage-
ment logic may notice that, after having initiated SMM to
power down one or more 110 devices, another several minutes
have elapsed without activity. Power management logic can
again assert SlVIT, the SMM service routine would obtain the
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