AMD AMD5K86 - TABLE 2-3. Cache States for Snoops, Invalidation, and Replacements

AMD~
18524B/O-Mar1996
AMD5,!J6 Processor Technical Reference Manual
TABLE 2-2. Cache States for Read and Write Accesses
Type
Tags
1
Cache State
Access Cache State After Access
Before
Type
2
Access
5
MESI State
5
Write back-
Write through
State
invalid single read invalid
invalid
Read
Linear
writethrough
Miss
invalid
3
burst read
shared or
or
Cache
(cache able)
(line fill)
exclusive
4
writeback
4
Read
shared shared write through
-
Read
Linear exclusive
exclusive writeback
Hit
-
modified
-
modified writeback
Write
Linear invalid single write
invalid invalid
Miss
Cache
cache
shared or
writethrough
Write
shared update and
exclusive
4
or
Write
Linear
single write
writeback
4
Hit
exclusive or
cache update
modified writeback
modified
Notes:
1. Linear tags are masked by A2OtlII, physical tags are not.
2.
Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32 bytes.
3. IfrACRE and7mV are Low.
4. If PWT is Low and WB;WT is High.
s MESI state is stored in the physical tags. Instruction-cache state consists only of valid (shared) or invalid, and there are no write-
related states.
- Not applicable or none.
Cache Organization and Management
2-19