AMD AMD5K86 - FIGURE 5-5. Single-Transfer Misaligned Memory and

AMD~
AMD5xB6 Processor Technical Reference Manual
18524B/O-Mar1996
Single-Transfer
Misaligned Memory
and I/O Transfers
5-148
Figure 5-5 shows a misaligned (split) memory read followed by
a misaligned I/O write. (For a definition of misaligned, see Sec-
tion 5.3.3 on page 5-139.) When the processor encounters a mis-
aligned access, it determines the appropriate pair of bus
cycles-each with its own ADS and BRDY -required to com-
plete the access.
In this example, the first pair of bus cycles represents a mem-
ory read of the doubleword at SOOEh. This access crosses a dou-
bleword boundary, so it is misaligned. The processor first reads
the word at SOOEh, followed by the word at SOlOh. The second
pair of bus cycles represents a write of a double word to I/O
address SEh. This transfer also crosses a doubleword bound-
ary, so it is misaligned. The processor writes the word to I/O
address 90h, followed by the word to I/O address SEh.
The AMD5
K
S6 processor performs misaligned memory read,
memory write, and I/O read transfers in the reverse order of
the Pentium processor, but misaligned I/O write transfers are
performed in the same order on both processors. Table 5-20
shows the order. Thus, in this example, the I/O write accesses
the most-significant bytes first followed by the least-significant
bytes, the opposite order from the memory accesses and I/O
reads.
TABLE 5-20. Bus-Cycle Order During Misaligned Transfers
Type of Access
First K5 Second K5
Pentium
Cycle
Cycle
Compatible?
Memory Read
LSBs MSBs no
Memory Write
LSBs MSBs
no
IJO Read
LSBs MSBs no
IJO Write MSBs LSBs
yes
The SCYC (Split Cycle) output has no meaning in unlocked
misaligned transfers. It is only meaningful in locked mis-
aligned transfers.
Bus Interface