AMD AMD5K86 - Bus Cycle Timing

AMD~
185248/0- Mar1996 AMD5~6 Processor Technical Reference Manual
5.4 Bus Cycle Timing
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles.
Only a representative set of bus cycles are illustrated. Many
more combinations are possible.
5.4.1
Timing Diagrams
Bus Cycle Timing
The timing diagrams show the signals on the external bus as a
function of time, as measured by the bus clock (CLK). Through-
out this chapter, the term clock refers to bus-clock cycles, not
processor-clock cycles, and the term cycle refers to bus cycles
not clocks. A clock extends from one rising CLK edge to the
next rising CLK edge. The processor samples and drives most
signals relative to the rising edge of CLK. The exceptions to
this rule include:
• FLUSH and "SMI-Sampled on the falling edge of CLK
• BF, FLUSH, FRCMC, and INIT -Sampled on the falling edge
of RESET
• TDI, TDO, TMS and TRST -Sampled relative TCK
For each signal in the timing diagrams, the High level repre-
sents 1, the Low level represents 0, and the middle level repre-
sents the floating (high-impedance) state. When both the High
and Low levels are shown, the meaning depends on the signal.
For a single signal, it means don't care. For a bus, it means that
the processor or system logic is driving a value, but this value
mayor may not be valid (for example, the value on the address
bus is valid only during the assertion of AUS, although
addresses are also driven on the bus at other times).
The value indicated for the address bus represents the value
driven on lines A31-A3. This value, multiplied by 8, is the byte
address of an 8-byte region in memory. The value for BE7-BEU
indicates which bytes in that region are to be transferred: the
bytes corresponding to the zeros on BE7-BEU are transferred.
The timing diagrams given in the following sections assume
that the current privilege level (CPL) is always o.
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