AMD AMD5K86 - Single-Transfer Reads and Writes

AMD~
AMD5xB6 Processor Technical Reference Manual 18524BjO-Mar1996
5.4.2 Single-Transfer Reads and Writes
Single-Transfer
Memory Read and
Write
5-142
The single-transfer memory and I/O bus cycles transfer 1, 2, 4,
or 8 bytes. Misaligned instructions or operands result in a split
cycle, which requires multiple transactions on the bus. During
single-transfer (non-cacheable) code fetches, the AMD5
K
86
and Pentium processors read 8 bytes, not 16 bytes as the 486
processor does.
Figure 5-2 shows a single-transfer double word code fetch
(read) from memory, followed immediately by a single-transfer
doubleword write to memory. For the memory-read cycle, the
processor drives A31-A3, BE7-BEU (with AP for parity check),
DfC, W/R, and MIIO. Then, somewhat later, it asserts ADS and
BREQ. ADS, which is held asserted for only one clock, vali-
dates the bus cycle. The processor then waits for system logic
to return the data on D63-DO (with DP7-DPO for parity check)
and assert BRDY. System logic can return BRDY as early as
one clock after ADS, thus supporting very fast memory
devices.
During the read cycle, the processor drives PCD, PWT, and
CACHE to indicate its caching and cache-coherency intent for
the access. System logic returns KEN and WBIWT to either con-
firm or change this intent. In this example, the processor
asserts PCD and negates CACHE, so the accesses are non-
cacheable, even though system logic asserts KEN during the
BRDYs to indicate its support for cacheability. The processor
(which drives CACHE) and system logic (which drives KEN)
must agree in order for an access to be cacheable. They must
also agree among PWT and WBIWT in order for a cacheable
line to be cached in the writeback state.
The processor can drive another cycle (in this example, a write
cycle) as early as two clocks after the assertion of BRDY. A
dead (or idle) clock is thus guaranteed between any two bus
cycles. As in the read cycle, neither the address nor the cycle-
definition signals are valid until the processor asserts ADS,
and the value driven on A31-A3 is valid only during the asser-
tion of ADS.
This example shows a parity error during the read cycle, as
indicated by the processor's assertion of PCHK two clocks
after BRDY. Because system logic asserts PEN during the
Bus Interface