AMD AMD5K86 - RDMSR and WRMSR

AMD~
AMD5J!36 Processor Technical Reference Manual
3.3.4
RDTSC
mnemonic
RDTSC
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
opcode description
OF31 Read time stamp counter
Selectable by TSD bit in CR4
EAX,EDX
none
Real, Virtual-8086 mode-Invalid Opcode
Protected mode-GP (0) if CPl not = 0 when CR4.TSD = 1
18524BjO-Mar1996
The processor's 64-bit time stamp counter (TSC) increments on each processor clock.
In Real or Protected mode, the counter can be read with the RDMSR instruction and
written with the WRMSR instruction when CPL = O. However, in Protected mode the
RDTSC instruction can be used to read the counter at privilege levels higher than
CPL = O.
The required privilege level for using the RDTSC instruction is determined by the
Time Stamp Disable (TSD) bit in CR4, as follows:
• CPL = O-Set the TSD bit in CR4 to 1
• Any CPL-Clear the TSD bit in CR4 to 0
The RDTSC instruction reads the counter value into the EDX and EAX registers as
follows:
• EDX-Upper 32 bits of TSC
•
~X - Lower 32 bits of TSC
The following example shows how the RDTSC instruction can be used. After this
code is executed, EAX and EDX contain the time required to execute the RDTSC
instruction.
J-J4
mov ecx,lOh
mov eax,OOOOOOOOh
db OFh, 30h
db OFh, 31h
db OFh, 31h
;Time Stamp Counter Access via MSRs
;Initialize the Counter to zero
;WRMSR
;RDTSC
;RDTSC
Software Environment and Extensions