AMD AMD5K86 - ADSC (Address Strobe Copy)

1 B524B/O-Mar1996
Signal Descriptions
AMD~
AMD5~6 Processor Technical Reference Manual
bus masters, thus intervening temporarily in the processor's
sequential operations.
If BUFF is asserted while ADS is asserted, ADS remains Low
(floats asserted). System logic must consider this when inter-
preting the state of ADS after negating BUFF. In the next clock
after BUFF is negated, the processor may reassert ADS to
restart a cycle if a cycle was aborted by the assertion of BUFF.
If system logic begins driving an inquire cycle by asserting
AHOLD or BUFF and then asserting EA1JS with the inquire
address, and the processor is driving a Branch-Trace Message
special bus cycle at the same time that AHOLD or BUFF is
asserted, the branch address information driven by the proces-
sor on A31-A3 can be overwritten by the inquiring bus master.
In such cases, system logic should latch A31-A3 when ADS is
asserted, before asserting AHOLD or BUFF.
At the falling edge of RESET, the states of BRDYC and nus::
"CHK control the drive strength on the A21-A3 (not including
A31-A22), ADS, HITM, and W/R signals. The drive strength is
weak for all states of BRDyC and BU SCHK except BRDYC and
BusCHK both Low (0), in which case the drive strength is
strong. The A31-A22 signals use the weak drive strength at all
times. See the data sheet for details.
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