AMD AMD5K86 - Page 145

AMD~
AMD5/36 Processor Technical Reference Manual
1 8524BjO-Marl 996
5-26
entries, the processor uses a pseudo-random algorithm to
select a line for replacement. If the selected line is cached in
the modified state, it must be written back to memory. In this
case, the order of events is:
1. Complete the burst read, placing the incoming cache line in
the processor's line fill buffer.
2. Write the modified line back to memory.
3. Fill the vacated cache line with the contents of the line
buffer.
Processor-initiated write backs can occur during cache line
replacement, internal snoops for self-modifying code, and exe-
cution of the WBINVD instruction. System-initiated writebacks
can occur during inquire cycle hits to modified cache lines
(while AHOLD, BUFF or HLDA is asserted) or by assertion of
the FLUSH input. The processor drives write backs by assert-
ing ADS and either reusing the inquire cycle address (if
AHOLD
is held asserted throughout the writeback) or driving
the address itself (if AHOLD is negated for the write back, or if
BUFF or HOLD was used to obtain the bus).
During an inquire cycle that hits a modified cache line, the
processor asserts ADS as soon as two clocks after asserting
HITlVI, regardless of whether AHOLD is asserted or negated.
By contrast, if BUFF or HLDA is asserted instead of AHOLD
during an inquire hit, the processor postpones the write back
until after BUFF or HLDA is negated.
During special bus cycles and interrupt acknowledge opera-
tions, the processor drives ADS to validate A31-A3, BE7-BEU
and the cycle definition signals. This use of ADS and A31-A3
simply serves to identify the type of special bus cycle, rather
than to address a location in memory or 1/0 space.
The processor asserts BREQ in the same clock that it asserts
ADS, although BREQ is also asserted at other times (see the
description of BREQ on page 5-46). The processor negates ADS
for one clock between any contiguous bus operations, such as
between a single-transfer 110 write and a burst read from mem-
ory, or between two burst reads. The same is true for contigu-
ous sequences of locked operations (sequences of locked bus
cycle pairs). System logic can use the negation of ADS between
contiguous bus operations to make the bus available to other
Bus Interface