AMD AMD5K86 - Data Cache

18524B/O- Mar1996
2.3.2
AMD~
AMD5xB6 Processor Technical Reference Manual
Parts of the current code-segment descriptor are maintained in
the instruction cache. This allows the cache to translate logical
addresses for branches and other prefetch targets to linear
address tags for the incoming cache-line fills.
Details on the instruction-cache storage formats and testing
are given in Section 7.4 on page 7-7.
Data Cache
The data cache has the following characteristics:
• 8 Kbytes
• 32-byte line size
• Four-way, set associative
• Four banks
• Dual-tagged (linear and physical)
• Byte-addressable
• Single-clock access
• Two true linear-tag ports-two parallel accesses per clock
• Two logical data ports (one read-only, one read/write)-two
parallel accesses per clock, if not to the same bank
• MESI cache-coherency protocol (maintained by physical
tags)
• Requested-word-first line-fill protocol
• Pseudo-random replacement policy
• Read/write (writeback or write through modes)
The data cache overcomes load/store bottlenecks by support-
ing simultaneous accesses to two lines in a single clock, if the
lines are in separate banks. Each of the four cache banks con-
tains eight bytes, or one-fourth of a 32-byte cache line. They
are interleaved on a four-byte boundary. One instruction can
be accessing bank 0 (bytes 0-3 and 16-19), while another
instruction is accessing bank 1, 2, or 3 (bytes 4-7 and 20-23,
8-11 and 24-27, and 12-15 and 28-31 respectively).
Entries in the data cache are real-state operands. A load occurs
when one of the load/store units reads an operand from the
data cache or memory. A store occurs at the retirement pipe-
line stage when an entry from the speculative-state store
Cache Organization and Management
2-15