AMD AMD5K86 - Cycle Definitions; Addressing

AMD~
AMD5J!l6 Processor Technical Reference Manual
18524B/O-Mar1996
5.3.2
5-1J8
Interrupt acknowledge operations consist of a locked pair of
read cycles. Special bus cycles are further differentiated by
the signals shown in Table 5-23 on page 5-181. In addition to
the processor-driven bus cycles shown in Table 5-19, system
logic can drive inquire cycles to the processor. These bus
cycles are described later, in Section 5.4.4 on page 5-157.
The processor samples BRDY during all bus cycles that it
drives. The number of BRDY s expected by the processor
depends on the type of bus cycle, as follows:
• One BRDY for an aligned single-transfer read or write
cycle, a special bus cycle, and each of two bus cycles in an
interrupt acknowledge operation. One additional BRDY for
each misaligned cycle.
• Four BRDY s for burst cycles (one BRDY for each of the four
transfers). Burst cycles are always aligned.
The last expected BRDY represents the completion of a proces-
sor-initiated bus cycle. The processor guarantees at least one
idle clock between consecutive bus cycles, whether unlocked
or locked. This means that consecutive locked operations,
which consist of consecutive bus cycles, also have at least one
idle clock between them.
Addressing
The address for a bus cycle is driven on A31-A3 and BID-BEU.
A31-A3 carry the upper 29 bits of the address, identifying an
aligned 8-byte (quadword) region in memory. BE7-BEU iden-
tify the accessed bytes in that quadword, in effect indicating
the three least-significant bits of the address and the size (in
bytes) of the desired transfer. For burst and inquire cycles,
A31-A5 are sufficient to identify the memory location of the
cache line. For burst reads, which are four-transfer cache-line
fills, system logic should watch A4-A3 and return the
addressed quadword first, before returning the remainder of
the cache line.
More details on burst-cycle addressing are given in Section
5.4.3 on page 5-150.
Bus Interface