AMD AMD5K86 - Illegal Instruction (Reserved Opcode)

AMD~
1 8524BjO-Marl 996 AMD51J6 Processor Technical Reference Manual
3.3.6 RSM
mnemonic
RSM
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
opcode description
OFAA Resume execution (exit System Management Mode)
CPL=O
CS, DS, ES, FS, GS, SS, EIP, EFLAGS, LDTR,
CR3, EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI
none
Real, Virtual-8086 mode-Invalid opcode if not in SMM
Protected mode-Invalid opcode if not in SMM
Protected mode-GP(O) if CPL not = 0
The RSM instruction should be the last instruction in any System Management Mode
(SMM) service routine. It restores the processor state that was saved when the sm
interrupt was asserted. This instruction is only valid when the processor is in SMM. It
generates an invalid opcode exception at all other times.
The processor enters the Shutdown state if any of the following illegal conditions are
encountered during the execution of the RSM instruction: the SMM base value is not
aligned on a 32-Kbyte boundary, or any reserved bit of CR4 set to 1, or the PG bit is
set while the PE is cleared in CRO, or the NW bit it set while the CD bit is cleared in
CRO.
New Instructions
3-37