AMD AMD5K86 - AHOLD-Initiated Inquire Hit to Modified Line

AMD~
AMD5#6 Processor Technical Reference Manual
18524B/O-Mar1996
AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
ClK
Figure 5-10 shows an example similar to Figure 5-9, minus the
address parity error, but this inquire cycle hits either a shared
or exclusive line in the cache, as indicated by the assertion of
HIT and the negation of IIITM two clocks after the assertion of
EADS. The processor invalidates the cache line because sys-
tem logic asserts INV with EADS. The processor may drive a
new bus cycle as early as one clock after system logic negates
AHOLD.
I
A31: CI~=;I==::i=: =r- =t-+ =_ =_ =t~}- -+-t _- -~E_~"--=-~~-=-~-=--=-~==~I ~
__ ~ ____ ~ ____ ~~,r~:----~----~--~----~----+-~\~~i ____ +1_
AHOLD
IlFl-EEO X
K'---+----'-~I
\'-~---,.---\I---;---'I i I
DjC
~
D63-DO
tAOS
RlT
RITN!
; ,I; i
~~i~~ __ ~~i
I \ :
INV
M/ID
W/R
ClK
Read Inquire
FIGURE 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
5-160
Bus Interface