AMD AMD5K86 - A31-A3 (Address Bus)

AMD~
AMD5~6 Processor Technical Reference Manual
18524BjO-Mar1996
5-20
paging mechanism. The operating system writes page table
entries so as to map all pages required for the Virtual-8086
mode task to addresses below 1 Mbyte.
Unlike the Pentium processor, the AMD5
K
86 processor ignores
AmM in Protected mode, Virtual-8086 mode, and System Man-
agement Mode (SMM). The Pentium processor masks the A20
bit if AmM is asserted in Protected mode or Virtual-8086
mode, even though this behavior is undefined and may change
in future processors. The AMD5
K
86 processor simply ignores
AmM except when the processor runs in Real mode.
The AMD5
K
86 processor applies AmM masking to its linear
cache tags, through which all programs access the caches.
Thus, assertion of A2UM affects all program-generated cache
addresses, including cache-line fills (caused by read misses),
cache writethroughs (caused by write misses or write hits to
lines in the shared state), and cache accesses that occur while
the processor does not control the bus. However, AmM does
not mask write backs or invalidations caused by internal
snoops, inquire cycles, the FLUsH signal, or the WBINVD
instruction-such addresses are looked up only in the physical
tags, which are not masked by AmM. (See Table 2-3 on page 2-
20 for details.) By contrast, the Pentium processor applies
masking only to physical addresses. This difference of masking
linear vs. physical addresses is not visible to software because
linear and physical addresses are identical in Real mode.
However, the AMD5
K
86 processor's AmM linear address mask-
ing can affect debug software differently than such masking on
the Pentium processor. With AmM asserted, the AMD5
K
86
processor does breakpoint matching (debug-register compari-
sons) on masked addresses, whereas the Pentium processor
<Ioes them on unmasked addresses.
Bus Interface