AMD AMD5K86 - Signal Descriptions; A20 M (Address Bit 20 Mask)

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AMD~

18524B/O-Mar1996

AMD5xB6

Processor

Technical

Reference

Manual

5.2.1

MoM

(Address

Bit

20

Mask)

Input

Summary

Sampled

Details

Signal

Descriptions

Assertion

of

A2ffiV[

causes

the

processor

to

clear

bit

20

of

the

A31-A3

address

bus

to

0

prior

to

accessing

the

cache

or

mem-

ory

in

Real

mode.

The

clearing

of

address

bit

20

bit

maps

addresses

above

1

Mbyte

to

addresses

below

1

Mbyte.

The

processor

samples

A2ffiV[

in

every

clock

during

Real

mode.

System

logic

can

drive

the

signal

either

synchronously

or

asyn-

chronously

(see

the

data

sheet

for

synchronously

driven

setup

and

hold

times).

:A:2UM:

is

sampled

only

in

Real

mode

during

memory

cycles

(including

cache

writethroughs

and

writebacks)

and

locked

cycles;

or

while

AHOLD,

BOFF,

HLDA,

RESET,

INIT,

or

PRDY

is

asserted.

:A:2UM:

is

not

sampled

when

the

processor

is

operat-

ing

in

Protected

mode,

Virtual-8086

mode

or

SMM;

during

110

cycles,

inquire

cycles,

special

bus

cycles,

or

interrupt

acknowl-

edge

operations;

or

while

the

processor

is

in

the

Shutdown,

Halt,

Stop

Grant,

or

Stop

Clock

states.

The

action

of

clearing

A20 so

that

addresses

above

1MB

wrap-

around

to

addresses

below

1

Mbyte

simulates

the

behavior

of

the

8086

processor,

allowing

the

processor

to

run

software

designed

for DOS.

:A:2UM:

should

only

be

asserted

when

the

pro-

cessor

runs

in

Real

mode.

:A:2UM:

should

not

be

asserted

during

the

first

code

fetch

follow-

ing

the

RESET

or

INIT

cycles

because

the

masking

of

bit

20

leads

to

a

fetch

from

an

incorrect

address.

The

BIOS

and

the

operating

system

alone

are

responsible

for

controlling

the

state

of:A:2UM:.

After

RESET

or

INIT,

they

do

this

by

writing

to

an

external

110

port.

(110

ports

60

and

64h,

or

port

92h,

or

regis-

ter-shadowed

versions

of

those

ports

are

commonly

used

to

control

the

state

of

:A:2UM:.)

The

instruction

pipeline

is

serial-

ized

by

virtue

of

writing

to

the

110

port,

thus

allowing

time

for

the

AZOlVI

signal

to

assert

before

the

next

memory

or

cache

access.

Advanced

operating

systems

that

do

not

run

under

DOS,

such

as

Windows

NTTM

and

OS/2

operating

systems,

do

not

use

Real

mode

and

never

assert

:A:2UM:.

Programs

running

in

Virtual-8086

mode

run

as

tasks

under

Pro-

tected

mode.

The

effect

of

:A:2UM:

for

these

Virtual-8086-mode

tasks

is

normally

emulated

by

the

operating

system

using

the

5-19

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