AMD AMD5K86 - Debug Registers

AMD~
AMD5J1J6 Processor Technical Reference Manual
18524B/O-Mar1996
7.5 Debug Registers
7.S.1
7.S.2
7-16
The processor implements the standard debug functions and
registers-DR7-DR6 and DR3-DRO (often called DR7-DRO)-
that are available on the 486 processor, plus an I/O breakpoint
extension.
Standard Debug Functions
The debug functions make the processor's state visible to
debug software through four debug registers (DR3-DRO) that
are accessed by MOV instructions. Accesses to memory
addresses can be set as breakpoints in the instruction flow by
invoking one of two debug exceptions (interrupt vectors 1 or 3)
during instruction or data accesses to the addresses. The debug
functions eliminate the need to embed breakpoints in code and
allow debugging of ROM as well as RAM.
For details on the standard 486 debug functions and registers,
see the AMD documentation on the Am486@ processor or other
commercial x86 literature.
1/0 Breakpoint Extension
The processor supports an I/O breakpoint extension for break-
points on I/O reads and writes. This function is enabled by set-
ting bit 3 of CR4, as described in Section 3.1 on page 3-2. When
enabled, the I/O breakpoint function is invoked by the follow-
ing:
• Entering the I/O port number as a breakpoint address (zero-
extended to 32 bits) in one of the breakpoint registers,
DR3-DRO
•
Entering the bit pattern, lOb, in the corresponding 2-bit
RfW field in DR7
All
data breakpoints on the AMDS
K
86 processor are precise,
including those encountered in repeated string operations,
which trap after completing the iteration on which the break-
point match occurs.
Test and Debug