AMD AMD5K86 - FIGURE 7-3. Test Formats: Data-Cache Tags; Array Test Data

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AMD5t136 Processor Technical Reference Manual
7.4.2
Array Pointer
Cache and TLB Testing
The array pointers entered in EDX (Figures 7-3 through 7-8,
top) specify particular array locations. For example, in the
data- and instruction-cache arrays, the way (or column) and set
(or index) in the array pointer specifies a cache line in the 4-
way, set-associative array. The array pointers for data-cache
data and instruction-cache instructions further specify a dword
location within that cache line. In the data cache, this dword is
32 bits of data. In the instruction cache, this dword is two
instruction bytes plus their associated pre-decode bits. For the
4-Kbyte TLB, the way and set specify one of the 128 TLB
entries. For the 4-Mbyte TLB, one of only four entries is speci-
fied.
Bits
7-0 of every array pointer encode the array [D, which iden-
tifies the array to be accessed, as shown in Table 7-3. To sim-
plify multiple accesses to an array, the contents of EDX is
retained after the RDMSR instruction executes (EDX is nor-
mally cleared after a RDMSR instruction).
TABLE 7-3. Array 105 in Array Pointers
Array Pointer
Accessed Array
Bits 7-0
EOh Data Cache: Data
Elh
Data Cache: Linear Tag
ECh
Data Cache: Physical Tag
E4h
Instruction Cache: Instructions
E5h
Instruction Cache: Linear Tag
EDh Instruction Cache: Physical Tag
E6h Instruction Cache: Valid Bits
E7h
Instruction Cache: Branch·Prediction Bits
E8h 4-Kbyte TLB: Page
E9h 4-Kbyte TLB: Linear Tag
EAh
4-Mbyte TLB: Page
EBh 4-Mbyte TLB: Linear Tag
7-9