AMD AMD5K86 - Bus Arbitration for Inquire Cycles

18524B/O-Mar1996
Cache
AMD~
AMD5~6 Processor Technical Reference Manual
entiate the function of an inquire cycle from the functions of
snoops and invalidations that work and/or are initiated in quite
different ways (see the preface for a short list of definitions).
For example, the AMD5
K
86 and Pentium processors support
only inquire cycles and internal snoops to their Ll cache. They
do not support continuous address bus watching.
The processor responds to inquire cycles by looking up the
inquire address in its physical tags. The physical-tag lookups
are done in parallel with the linear-tag lookups that support
program execution, so inquire cycles do not normally affect
processor performance. Even when inquire cycles hit modified
lines, which require writebacks to memory, only the proces-
sor's use of the bus is potentially affected. It can normally con-
tinue to operate out of its cache during a writeback.
Inquire cycles are initiated with EAIJS, INV, and an inquire
address on A31-A5. In response, the processor asserts HIT if
the inquire cycle address matches the address of a valid line in
the instruction or data cache, or it asserts both HIT and HITlVI
if the address matches a modified line in the data cache. If
HITlVI is asserted, the processor writes the modified line back to
memory. If INV was asserted with EAIJS, a hit invalidates the
line. If INV was negated with EAIJS, a hit leaves the line in the
shared state, or transitions it from the modified to shared state.
On the AMD5
K
86 processor, the maximum inquire or invalida-
tion rate with inquire cycles is one every two clocks, because
HIT and HITlVI change state two clocks after EAIJS, and EAIJS
can be asserted in the same clock in which HITlVI is negated.
The MESI-state transitions for inquire cycles, internal snoops,
and cache invalidations are given in Table 2-3 on page 2-20 and
Table 5-11 on page 5-73.
System logic typically drives inquire cycles to the processor
during memory accesses by another bus master. If the proces-
sor has a look-through L2 cache, inquire cycles need be driven
to the processor only when a prior inquire cycle hits in the pro-
cessor's L2 cache, or during line replacements in the proces-
sor's L2 cache. To implement inquire cycles to the processor or
L2 cache for every memory access by another caching master,
system logic can generate EAIJS using the equivalent of ADS
from the other caching master.
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