AMD AMD5K86 - AHOLD Arbitration

18524BjO- Mar1996
AHOLD Arbitration
Cache
AMD~
AMD5J116 Processor Technical Reference Manual
AHOLD's sole function is to support inquire cycles. The asser-
tion of AHOLD by system logic only gets control of the address
bus, leaving the data bus available to the processor for the
completion of an in-progress bus cycle. If an inquire cycle hits
a modified line while AHOLD is asserted, the writeback can
occur while AHOLD is either asserted or negated.
AHOLD is useful primarily in systems with multiple buses and
multiple bus masters, where operations can occur on the sepa-
rate buses independently and in parallel, and system logic
would drive separate AHOLD signals to each caching master.
This configuration occurs, for example, if the processor shares
its bus only with a look-through L2 cache, and other caching
masters work in parallel on a system bus that is isolated by sys-
tem logic from the L2 cache controller. Figure 6-4 shows such a
design.
A
typical sequence for inquire cycles that hit modified lines in
the processor's cache might be as follows:
1. The master on the system bus requests access to memory.
2. System logic responds by asserting BUFF to the processor's
L2 cache controller.
3. System logic drives an inquire cycle (represented by EADS)
to the L2 controller.
4. The L2 controller responds with III'rM to system logic
(assuming the addressed location is cached by the L2).
5. System logic asserts BUFF to the requesting master on the
system bus. (1II'rM from the L2 controller can be used to
generate BUFF to the other master.)
6. The L2 controller asserts AHOLD to the processor.
7. The L2 controller drives an inquire cycle (represented by
EADS) to the processor.
8. The processor responds with III'rM to the L2 controller,
indicating that the processor may have a later copy of the
location than does the L2 cache.
9. System logic negates BUFF to the L2 cache controller so
that the processor can write back its modified line to mem-
ory and the L2 cache.
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