AMD AMD5K86 - FIGURE 3-6. EFLAGS Register; TABLE 3-4. Virtual-Interrupt Additions to EFLAGS Register

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AMD5J!J6 Processor Technical Reference Manual
18524BjO-Mar1996
3-14
protection exception with error code zero, thereby notifying
the operating system that the program is now prepared to
accept the interrupt.
Thus, when VME extensions are enabled, the VIF and VIP bits
are set and cleared as follows:
• VIP-This bit is controlled by the processor and used by the
operating system to determine whether an external
maskable interrupt should be passed on to the program or
held pending. VIF is set and cleared for instructions that
can modify IF, and it is cleared during software interrupts
through interrupt gates. The original IF value is preserved
in the EFLAGS image on the stack.
• VIP-This bit is set and cleared by the operating system via
the EFLAGS image on the stack. It is set when an interrupt
occurs for a Virtual-8086 program who's VIF bit is cleared.
The bit is checked by the processor when the program sub-
sequently attempts to set VIF.
Figure 3-6 and Table 3-4 show the VIF and VIP bits in the
EFLAGS register. The VME extensions support conventional
emulation methods for passing interrupts to Virtual-8086 pro-
grams, but they make it possible for the operating system to
avoid time-consuming emulation of most instructions that
write or read the IF.
The VIF and IF flags only affect the way the operating system
deals with hardware interrupts (the INTR signal). Software
interrupts are handled like machine-generated exceptions and
cannot be masked by real or virtual copies of IF (see page 3-
21). The VIF and VIP flags only ease the software overhead
associated with managing interrupts so that virtual copies of
the IF flag do not have to be maintained by the operating sys-
tem. Instead, each task's TSS holds its own copy of these flags
in its EFLAGS image.
Software Environment and Extensions