AMD AMD5K86 - Virtual-8086 Mode Extensions (VME)

AMD~
18524B/O-Marl996 AMD51J6 Processor Technical Reference Manual
TABLE 3-3. Page-Table Entry (PTE) Fields
Bit
Mnemonic Description
Function
31-12
BASE
Physical Base
The physical base address of a 4-Kbyte page.
Address
Software may use the field to store any type of
11-9
AVL
Available to
information. When the page-table entry is not
Software
present (P bit cleared), bits 31-1 become available
to software.
8 G Global o = local, 1 = global.
This bit is ignored in page-table entries, although
7
PS
Page Size clearing it to 0 preserves consistent usage of this
bit between page-table and page-directory entries.
The processor sets this bit to 1 during a write to
6
D
Dirty
the page that is mapped by this page-table entry.
o = not written, 1 = written.
The processor sets this bit to 1 during a read or
5
A Accessed
write to any page that is mapped by this page-
table entry.
o = not read or written, 1 = read or written.
Specifies cacheability for all locations in the page
Page Cache
mapped by this page-table entry. Whether a loca-
4
PCD
tion is actually cached also depends on several
Disable
other factors.
o = cache able page, 1 = non-cacheable.
Specifies writeback or write through cache proto-
col for all locations in the page mapped by this
3 PWT
Page
page-table entry. Whether a location is actually
Writethrough
cached in a writeback or writethrough state also
depends on several other factors.
o = write back, 1 = writethough.
2
DIS
D serlSupervi-
0= user (any CPL), 1 = supervisor (CPL < 3).
sor
1 WIR
WritelRead
o = read or execute, 1 = write, read, or execute.
0
P Present o = not valid, 1 = valid.
Control Register 4 (CR4) Extensions
J-l1