AMD AMD5K86 - Bus Signal Compatibility with Pentium Processor

AMD~
18524B/O-Mar1996
AMD5J!36 Processor Technical Reference Manual
TABLE 5-3. Summary of Interrupts and Exceptions
Priority Description
Type SamplingS
Vector
l
Acknowledgment
Point of Interruptibility6
1
2
3
4
5
6
7
8
9
Notes:
1.
2.
3.
4.
5.
6.
7.
INTn instruc-
tions and all
exceptions internal
0-255
none Entry to service routine.
other software
exceptions
BUSLRK
interrupt level-sensitive
18
2
none
Entry to service routine.
2
R/5
interrupt level-sensitive
none PRDV
Negation of PRDV.
FillSH-Acknowl-
BlIDY of FIDSR Acknowl-
FIDSR interrupt
edge-triggered
4
none edge special
edge bus cycle.
bus cycle
5Ml interrupt
edge-triggered
4
SMM3
5MJALr
Entry to SMM service
routine?
INIT interrupt
edge-triggered
4
BIOS none
Completion of
initialization.
NMI interrupts: IRET from
NMI interrupt
edge-triggered
4
2 none
service routine. All others:
Entry to service routine.
Interrupt acknowl-
INTR interrupt level-sensitive 0-255
edge specia I
Entry to service routine.
bus cycle
5TPITK
interrupt level-sensitive
none
Stop-Grant
Negation of STPITK.
special bus cycle
For interrupts with vectors, the processor saves its state prior to accessing service routine and changing program flow. Interrupts
without vectors do not change ferogram flow; instead, they simply pause program flow for the duration of the interrupt fundion
and then return to where they eft off.
If the machine check enable (MCE) bit in CR4 is set to 1.
The entry point for the 5Ml interrupt handler is at offset BOOOh from the 5MM Bose Address.
Only the edge-triggered interrupts are latched when asserted. All interrupts are recognized at the next instruction retirement
boundary.
If a bus cycle is in progress, FWEJE must be asserted before the interrupt is recognized.
For external interrupts (most exceptions, by contrast are recdi,nized when they occur). External interrupts are recognized at
instruction boundaries. MOVor POP instructions that load 55 elay interruptibility until after the next instruction, thus allowing both
55 and the corresponding 5P to load.
After assertion of5Ml, subsequent assertions of5Ml are masked so as to prevent recursive entry into 5MM. Other exceptions or
interrupts (except INIT and NMI), however, will intervene in the 5MM service routine.
The processor recognizes BUFF, HOLD, and AHOLD while any
interrupt signal is asserted, and
these signals will intervene
with their normal timing in the handling of any interrupt or
exception. The interrupt or
exception continues from where it
left off after the intervening signal is negated. For example, if
BUFF is asserted while a FLUSH operation is writing modified
Signal Overview
5-17