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AMD AMD5K86 - Bus Mastering Operations (including Snooping)

AMD AMD5K86
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AMDl'
AMD5J116
Processor
Technical
Reference
Manual
18524BjO-Mar1996
A.3
A.3.1
Comments
A.3.2
A-8
Bus
Mastering
Operations
(including
Snooping)
AHOLD
Snoop
to
Linefill
Buffer
Prior
to
or
Coincident
with
the
Establishment
of
the
Cacheability
of
the
Line
An
AHOLD
snoop
to
the
linefill
buffer
occurs
during
a
line
fill
when
the
address
of
the
snoop
matches
the
address
of
the
line-
fill.
If
the
snoop
happens
before
or
coincident
with
the
estab-
lishment
of
the
cache
ability
of
the
line
via
the
KEN
pin
sampled
with
the
assertion
of
NA
or
BRDY
(whichever
comes
first),
the
AMDS
K
86
processor
treats
the
snoop
as
a
hit,
whereas
the
Pentium
processor
treats
it
as
a miss.
In
treating
the
snoop
as
a
hit,
the
AMDS
K
86
processor
asserts
the
HIT
pin
and
also
caches
the
line
as
either
shared
or
invalid,
depending
on
the
state
of
the
INV
pin.
If
KEN
is
sampled
inac-
tive,
the
line
is
not
cached,
regardless
of
the
state
of
the
INV
pin.
In
treating
the
snoop
as a miss,
the
Pentium
processor
deas-
serts
the
HIT
pin
and
caches
the
line
based
on
KEN, WBIWT,
and
PWT
in
the
same
way
it
does
for
line
fills
with
no
snoop.
The
behavior
of
snoops
to
the
line
fill
buffer
after
cacheability
is
determined
is
described
in
Section
A.3.2.
BUFF
Asserted
before
Snoop
to
Linefill
Buffer
and
after
the
Cacheability
of
the
Line
is
Established
A
snoop
to
the
linefill
buffer
occurs
during
a
linefill
when
the
address
of
the
snoop
matches
the
address
of
the
linefill.
If
BUFF
is
asserted
after
the
cache
ability
of
the
line
is
deter-
mined
via
the
KEN
pin
being
sampled
active
(with
the
asser-
tion
of
NA
or
BRDY,
whichever
comes
first)
and
a
snoop
to
the
line
fill
buffer
occurs
with
either
BUFF
or
AHOLD
or
both
asserted,
the
Pentium
processor
treats
the
snoop
as a
hit,
whereas
the
AMDS
K
86
processor
mayor
may
not
treat
it
as
a
hit.
For
DCACHE
linefills,
the
AMDS
K
86
processor
treats
the
snoop
as
a miss.
For
ICACHE
linefills,
the
AMDS
K
86
processor
may
treat
the
snoop
as
a
hit
or
a miss,
because
the
speculative
nature
of
the
line
fills
makes
their
cacheability
dependent
on

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