AMD AMD5K86 - FIGURE 6-6. Clock Control State Transitions

18524BjO- Mar1996
Clock Control
AMD~
AMD5JJ6 Processor Technical Reference Manual
state, and it returns to the Halt state when STPCLK is negated.
No processor registers are saved before entering the Halt state
because the processor returns to the next unexecuted instruc-
tion in program order when it returns to its prior operating
mode. When the processor returns to the Halt state, the HLT
instruction is not refetched but the processor drives the Halt
special bus cycle on the bus after the return.
Within the Halt state, the processor disables the majority of its
internal clock distribution and (if sTpCLK is asserted) the
internal pullup resistor on STPCLK. However, its phase-lock
loop still runs, its key internal logic is still clocked, most of its
inputs and outputs retain their last state (except D63-DO and
DP7-DPO which are floated), and it still responds to input sig-
nals.
The HLT instruction is commonly executed by modern UNIX-
type operating systems as a method of entering an idle loop.
The operating system sees that it has no pending processes,
therefore nothing to execute, so it executes HLT. Entry into
the Halt state achieves the same power-saving effect as entry
into the Stop Grant state, but the method is simpler and faster.
Entry into the Halt state requires only the execution of the
HLT instruction, whereas entry into the Stop Grant state
requires that system logic monitor system activity, assert SIT-
'CLK, and decode the processor's acknowledgment (potentially
several clocks later) via the Stop Grant special bus cycle.
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