AMD AMD5K86 - Hardware Configuration Register (HWCR)

AMD~
18524BjO-Mar1996 AMD5xB6 Processor Technical Reference Manual
7.1 Hardware Configuration Register (HWCR)
31
_ Reserved
Disable Data Cache
Disable Instruction Cache
Disable Branch Prediction
Debug Control
000 Off
The Hardware Configuration Register (HWCR) is a model-spe-
cific
register (MSR) that contains configuration bits that
enable cache, branch tracing, debug, and clock control func-
tions. The WRMSR and RDMSR instructions access the HWCR
when the ECX register contains the value 83h, as described in
Section 3.3.5 on page 3-35. Figure 7-1 and Table 7-1 show the
format and fields of the HWCR.
DDC
DIC
DBP
DC
876 543 2 1 a
;, -----'III I
001 Enable branch trace usages
100 Activate Probe mode on debug trap
Disable Stopping Processor Clocks DSPC a
FIGURE 7-1. Hardware Configuration Register (HWCR)
Hardware Configuration Register (HWCR) 7-J