AMD~
AMD5t1J6
Processor
Technical
Reference
Manual
18524BjO-Mar1996
TABLE
7-4.
Branch-Trace
Message
Special
Bus
Cycle
Fields
Signals First Special Bus Cycle Second Special Bus Cycle
A31
0=
first special bus cycle (source) 1 = second special bus cycle (target)
Operating Mode of Target:
11
= Virtual-8086 Mode
A30-AZ9 not valid 10 = Protected Mode
01
= not valid
00
= Real Mode
Default
Operand Size of Target Segment:
AZ8
not valid
1 =
3Z-bit
0=
16-bit
A27-AZO
0 0
A19-A4
Code Segment (CS) selector of
Code Segment (CS) selector of Branch
Branch Source.
Target.
A3
0 0
D31-DO
EIP of Branch Source. EIP of Branch Target.
7.7
Functional-Redundancy
Checking
7-18
If
FRCMC is
asserted
at
RESET,
the
processor
enters
Func-
tional-Redundancy
Checking
mode
as
the
checker,
and
reports
checking
errors
on
the
IERR
output.
If
FRCMC
is
negated
at
RESET,
the
processor
operates
normally,
although
it
also
behaves
as
the
master
in
a
functional-redundancy
checking
arrangement
with
a
checker.
In
the
Functional-Redundancy
Checking
mode,
two
processors
have
their
signals
tied
together.
One
processor
(the
master)
operates
normally.
The
other
processor
(the
checker)
has
its
output
and
bidirectional
signals
(except
for TDO
and
IERR)
floated
to
detect
the
state
of
the
master's
signals.
The
master
controls
instruction
fetching
and
the
checker
mimics
its
behav-
ior
by
sampling
the
fetched
instructions
as
they
appear
on
the
bus.
Both
processors
execute
the
instructions
in
lock
step.
The
checker
compares
the
state
of
the
master's
output
and
bidirec-
tional
signals
with
the
state
that
the
checker
itself
would
have
driven
for
the
same
instruction
stream.
Test
and
Debug
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