AMD AMD5K86 - TABLE 5-9. MESI-State Transitions for Reads

18524BjO- Mar1996
Signal Descriptions
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AMD5116 Processor Technical Reference Manual
during write hits to shared cache lines and during write misses,
but writethroughs are driven as single transfers of 1 to 8 bytes.
CACHE is not asserted during writethroughs.
CACHE is partially determined by the PCD bit maintained by
the operating system (in Protected mode, for example, the
PCD bit is maintained in the page directory and page table
entries for the accessed page). This is the bit that fully deter-
mines the processor's page cache disable (PCD) output. PCD
indicates a non-cache able page. Thus, the states of CACHE and
PCD are very often the same. CACHE is never asserted when
PCD is asserted. PCD indicates the cache ability of an entire
page, and CACHE indicates the burstability of a particular bus
cycle; burstability is a necessary but insufficient condition for
determining cache ability. The cacheability of a particular bus
cycle is determined during read cycles when system logic
asserts KEN while the processor asserts CACHE. KEN is not a
factor in determining the state of the PCD or CACHE signals.
The processor drives both PCD and CACHE before it knows
the state of KEN. For details, see the descriptions of KEN and
PCD on pages 5-90 and 5-100.
The MESI state of a cache line is determined at the time of the
line-fill by the states of the CACHE, KEN, PWT and WBfWT
signals. Table 5-9 shows the relationship between these signals
and the data cache MESI states during reads. Read misses with
CACHE or KEN negated are non-cache able and are driven as
single-transfer cycles on the bus. Read misses with both
CACHE and KEN asserted in the first transfer of the bus cycle
are cacheable, are driven as burst cycles on the bus, and have
their resulting MESI state determined by PWT and WB/WT.
Read hits have their resulting MESI state determined entirely
by their prior MESI state.
For data cache MESI state transitions during writes, see the
description of the WBfWT signal on page 5-134. For more
details on data-cache MESI state transitions and control, and
the correspondence between MESI states and writeback or
writethrough states, see Section 5.2.56 on page 5-134 and Sec-
tion 6.2 on page 6-8.
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