AMD AMD5K86 - CACHE (Cacheable Access)

AMD~
AMD5J!36 Processor Technical Reference Manual
18524BjO-Mar1996
5.2.15
Summary
CACHE (Cacheable Access)
output
The processor drives CACHE to specify that the current bus
cycle is a burst cycle. If CACHE is asserted for a read cycle, the
cycle is a four-transfer burst and fills a cache line. If CACHE is
asserted for a write cycle, the cycle is a four-transfer burst
writeback of a modified cache line. CACHE is not asserted for
writethroughs, so the signal is not asserted for all cycles involv-
ing cacheable locations.
Driven and Floated
The processor drives CACHE from ADS until the last expected
BRDY of the bus cycle.
Details
5-50
CACHE is driven during memory cycles, I/O cycles, locked
cycles, special bus cycles, and interrupt acknowledge opera-
tions in the normal operating modes (Real, Protected, and Vir-
tual-8086)
and in SMM. CACHE is not driven in the Shutdown,
Halt, or Stop Grant states, except for writebacks due to inquire
cycles, and CACHE is never driven during the Stop Clock state
or while BUFF, HLDA, RESET, INIT, or PRDY is asserted.
The processor floats CACHE one clock after system logic
asserts BUFF and in the same clock that the processor asserts
HLDA.
The processor asserts CACHE for certain types of unlocked
memory reads, as specified by the operating system, and for all
writebacks (writes of lines cached in the M state). The asser-
tion of CACHE indicates the processor's intent to drive the
read or write cycle as a 32-byte burst and, in the case of read
cycles, to cache the data or instructions. During reads, system
logic can use the assertion of CACHE to initiate a table lookup
of cache able addresses. To enable caching in the processor's
instruction or data cache, system logic must assert KEN during
the first BRDY or NA of the bus cycle, whichever comes first. If
either CACHE or KEN is negated when KEN is sampled, the
processor performs a non-cache able, single-transfer read.
The only type of write cycle for which the processor asserts
CACHE are 32-byte write backs of modified data. Writebacks
can be caused by (a) externally initiated inquire cycles or
FLUSH operations, (b) processor-initiated internal snoops or
cache line replacements, or (c) program-initiated WBINVD
instructions. By contrast, the processor drives writethroughs
Bus Interface