AMD AMD5K86 - Global Pages

AMD~
AMD5/J6 Processor Technical Reference Manual
1 8524B/O-Mar1996
TABLE 3-2. Page-Directory Entry (POE) Fields
Bit Mnemonic Description
Function
For 4-Kbyte pages, bits 31-12 contain the physical
base address of a 4-Kbyte page table.
31-12 BASE
Physical Base
For 4-Mbyte pages, bits 31-22 contain the physical
Address
base address of a 4-Mbyte page and bits 21-12
must be cleared to o. (The processor will generate
a page fault if bits 21-12 are not cleared to 0.)
Software may use this field to store any type of
11-9
AVL
Available to information. When the page-directory entry is not
Software
present (P bit cleared), bits 31-1 become available
to software.
8 G Global
0= local, 1 = global.
7 PS Page Size
o = 4-Kbyte, 1 = 4-Mbyte.
For 4-Kbyte pages, this bit is undefined and
ignored. The processor does not change it.
o = not written, 1 = written.
6
D Dirty
For 4-Mbyte pages, the processor sets this bit to 1
during a write to the page that is mapped by this
page-directory entry.
o = not written, 1 = written.
The processor sets this bit to 1 during a read or
5 A Accessed
write to any page that is mapped by this page-
directory entry.
o = not read or written, 1 = read or written.
Specifies cache ability for all pages mapped by this
Page Cache Dis-
page-directory entry. Whether a location in a
4
PCD
mapped page is actually cached also depends on
able
several other factors.
o = cacheable page, 1 = non-cacheable.
Specifies write back or writethrough cache proto-
col for all pages mapped by this page-directory
3
PWT
Page
entry. Whether a location in a mapped page is
Write through
actually cached in a writeback or write through
state also depends on several other factors.
o = writeback page, 1 = write though page.
2 D/S
D ser/Supervisor 0= user (any CPL), 1 = supervisor (CPL < 3).
1
W/R Write/Read o = read or execute, 1 = write, read, or execute.
0
P Present o = not valid, 1 = valid.
J-8 Software Environment and Extensions