AMD AMD5K86 - Result

18524BjO-Mar1996
2.2.4 Result
Execution Pipeline
AMD~
AMD5i<!J6 Processor Technical Reference Manual
The branch unit receives branch-prediction information from
the decoder. If the branch unit executes a branch differently
than predicted, it signals the instruction cache, reorder buffer,
and decode logic, and it passes the correct information to the
branch-prediction array in the fetch stage.
The processor implements a 16-entry reorder buffer (ROB) for
speculative-state register renaming, and a 4-entry store buffer
for speculative-state buffering between the load/store units
and the data cache. An Rap is said to complete when the result
of its execution is written to the ROB or store buffer. Results
may be returned out of order. Results written to the ROB are
simultaneously forwarded (that is, fed back) to all execution
units.
An entry tag is allocated at the top of the ROB for each Rap
that is dispatched to a reservation station. Entries for up to
four Raps can be allocated simultaneously. Among other
things, the ROB keeps track of the program counter associated
with each instruction, resolves RaP-level dependencies, stores
speculative results, provides the most recent copy of a register
to execution units, recovers from mispredicted branches with-
out altering real state, and provides substitute tags to internal
resources when required operands are still outstanding.
The x86 architecture defines only eight general-purpose regis-
ters and eight entries in the floating-point stack. This limited
set of registers leads to register dependencies and register
reuse. The processor overcomes register dependencies by
renaming registers in the ROB, and it overcomes register reuse
with data forwarding. Data forwarding provides execution
results immediately to other instructions without waiting for
results to be written to and read back from registers, the data
cache, or memory. Multiple speculative-state registers for each
real-state register enable different execution units to use the
same logical register simultaneously. When the register file
detects multiple writes to the same real-state register, only the
latest write in program order is performed-all other writes
are discarded. Multiple reads of the same real-state register
are performed without detection or special handling.
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