AMD AMD5K86 - W;R (Write or Read)

AMD~
AMD5~6 Processor Technical Reference Manual
18524BjO-Marl996
5.2.54
Summary
Sampled
Details
5-1J2
TRST (Test Reset)
Input
The assertion of TRST initializes the Test Access Port (TAP) by
resetting its state machine.
TRST is an asynchronous input. Unlike other asynchronous
inputs, no synchronous setup and hold time are specified for
TRST. TRST has an internal pullup resistor.
TRST is always sampled, except while RESET or INIT is
asserted.
When TRST is asserted, the TAP controller enters its test-
reset-logic
state, regardless of the controller state. This action
is the same as that achieved by holding TMS asserted for five
or more clocks. The assertion of TRST is unnecessary at
RESET because the processor performs the TAP reset auto-
matically at that point.
See the IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1) specification for a description of
how the TAP signals and instructions are used for testing.
Bus Interface