AMD AMD5K86 - BF (Bus Frequency); TABLE 5-7. Processor-To-Bus Clock Ratios

AMD~
AMD5~6 Processor Technical Reference Manual
18524B/O-Mar1996
ships. This function of BE7-BEU bears no relationship to the
D63-DO data bus. This is particularly apparent in the case of
the Branch-Trace Message special bus cycle, during which the
value of BE7-BEU is DFh (llOl_llllb) but, in contradiction to
the byte-enable bits, the four bytes on D3l-DO carry valid data
during both cycles of the operation: during the first cycle, D3l-
DO carries the EIP value of the source (branch) instruction;
during the second cycle, D3l-DO carries the EIP value of the
branch-target instruction.
TABLE 5-6. Encodings For Special Bus Cycles
BE7-BEU A31-A3
Special Bus Cyele
t
Cause
Notes:
I.
2.
5-J6
FEh
... 00h Shutdown Triple fault
FDh ... 00h
Cache Invalidation
INVD instruction
FBh ... 10h Stop Grant STPCLK
FBh
... 00h Halt HLT instruction
F7h
... 00h
Cache Writeback and
WBINVD instruction
Invalidation
EFh ... 00h FLUSH Acknowledge FLUSH
Bit 5 = 1 and bits 3-1 = 001 in
DFh ... 00h
Branch-Trace Message
2
the Hardware Configuration
Register (HWCR). See Section
7.1 on page 7·3 for details.
For all special bus cycles, D/C = 0, M/fO = a and Wj'l? = I. System logic must return lJlIDY in response to this cycle.
The message in a branch-trace message special bus cycle is different in the AMD5r.B6 and Pentium processors.
Certain models of the Pentium processor implement BE7-BE5
as outputs and BE4-BEU as bidirectional signals. On the
AMD5
K
86 processor, however, all eight BE7-BEU signals are
outputs only.
Bus Interface