AMD AMD5K86 - Exceptions and Interrupts in SMM

AMD~
18524BjO-Mar1996 AMD5JJ6 Processor Technical Reference Manual
6.3.6 I/O Trap Dword
6.3.7
If the assertion of SMris recognized on the boundary of an I/O
instruction, the I/O trap dword at offset FF A4h in the SMM
state-save area contains information about the instruction. The
fields of the I/O trap dword are configured as follows:
• Bits 31-16-I/0 port address
• Bits 15-2-reserved
• Bit 1- Valid I/O instruction (1 = valid, 0 = invalid)
• Bit O-Input or output instruction (1 = INx, 0 = OUTx)
The I/O trap dword is related to the I/O trap restart slot,
described below. Bit 1 of the I/O trap dword (the valid bit)
should be tested if the I/O trap restart slot is to be changed.
I/O Trap Restart Slot
The I/O trap restart slot at offset FFOOh in the SMM state-save
area specifies whether the assertion of sm was recognized on
the boundary of an I/O instruction, and if so, whether the
trapped I/O instruction should be re-executed on return from
SMM. This is sometimes called the liD-instruction restart func-
tion.
Re-executing a trapped I/O instruction is useful, for exam-
ple, if an I/O write to disk finds the disk powered down. The
system logic monitoring such an access can assert sm. Then
the SMM service routine would query system logic, find a
failed I/O write, take action to power-up the I/O device, enable
the I/O trap restart slot feature, and return.
The fields of the I/O trap restart slot are configured as follows:
• Bits 31-16-reserved
• Bits 15-0- I/O instruction restart on return from SMM:
OOOOh = execute the next instruction after the trapped I/O
instruction
OOFFh = re-execute the trapped I/O instruction
The processor initializes the I/O trap restart slot to OOOOh upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap dword at
offset FF A4 in the SMM state-save area, as described in Sec-
System Management Mode (SMM)
6-31