AMD AMD5K86 - Buffers

AMD5J!16 Processor Technical Reference Manual
1 8524BjO-Marl 996
TABLE 2-4. Snoop Action
Origin of
Snoop
Type of Access
Instruction
Miss
Cache
Hit
Miss
Snooping Action
Instructions
Instruction
Cache
Prefetch
Cache
Data
Cache
Data
Store Write back
Buffer Buffers
yes!
yes
2
no
Internal
Read
Data
Hit
no no
Cache
Write
Miss
yes
4
yes
4
Write
Hit
no no
Notes:
I. The processor's response to a snoop hit depends on the state of the INV input signal and the state of the cache line as follows:
For instructions if INV is negated, the line remains invalid or shared, but if INV is asserted, the line is invalidated. For data if INV is
negated, valid lines remain in or transition to the shared state, a modified data cache line is written back before the line is marked
shared (with FfTT/flI asserted), invalid lines remain invalid.
For data if INV is asserted, the line is marked invalid. Modified lines are written back before invalidation.
2. If the snoop hits a line in the data cache, store buffer or writeback buffer, the line is written back (if modified) and invalidated.
Then the instruction-cache read is performed again. If the line is modified, a copy of the writeback data is passed directly to the
instruction cache, thus avoiding a line-fill bus cycle after the writeback bus cycle.
3. If the snoop hits a line in the instruction cache, prefetch cache, or line-fill buffer, the line stays valid and the data-cache read is
performed again, but as a single, non-cacheable read.
4. If the snoop hits a line in the instruction cache, prefetch cache, or line-fill buffer, the line is invalidated and the data-cache write is
performed.
- Not applicable.
Internal Snooping
2-22
The processor automatically snoops its instruction cache dur-
ing read or write misses to its data cache, and it snoops its data
cache during read misses to its instruction cache. It does this to
detect the presence of self-modifying code. Table 2-4 summa-
rizes the actions taken during this internal snooping.
Internal Architecture