AMD AMD5K86 - TABLE 3-2. Page-Directory Entry (PDE) Fields

18524B/0- Mar1996
31
Available to Software
Global
Page Size
Dirty = 0
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
AMD~
AMD5t!36 Processor Technical Reference Manual
Figure 3-1 and Table 3-1 show the fields in CR4. Figure 3-4 and
Table 3-2 show the fields in a page-directory entry.
4-Kbyte page translation differs from 4-Mbyte page translation
in the following ways:
• 4-Kbyte Paging (Figure 3-2)-Bits 31-22 of the linear address
select an entry in a 4-Kbyte page directory in memory,
whose physical base address is stored in CR3. Bits 21-12 of
the linear address select an entry in a 4-Kbyte page table in
memory, whose physical base address is specified by bits
31-22 of the page-directory entry. Bits 11-0 of the linear
address select a byte in a 4-Kbyte page, whose physical base
address is specified by the page-table entry.
• 4-Mbyte Paging (Figure 3-3)-Bits 31-22 of the linear
address select an entry in a 4-Mbyte page directory in mem-
ory, whose physical base address is stored in CR3. Bits 21-0
of the linear address select a byte in a 4-Mbyte page in
memory, whose physical base address is specified by bits
31-22 of the page-directory entry. Bits 21-12 of the page-
directory entry must be cleared to o.
Physical Base Address
AVL
11-9
G 8
PS 7
D
6
A
PCD 4
PWT 3
U/S
2
W/R
P 0
12 11 10 9 8 7 6 5 4 3 2 1 0
A
V
L
------11111
FIGURE 3-4. Page-Directory Entry (POE)
Control Register 4 (CR4) Extensions
J-7