AMD AMD5K86 - EADS (External Address Strobe)

AMD~
AMD5J!J6 Processor Technical Reference Manual 18524B/O-Mar1996
5.2.19 DP7-DPO (Data Parity)
Bidirectional
Summary
Driven, Sampled, and
Floated
Details
5-58
DP7-DPO carry the even-parity bits for each byte driven and
sampled on the D63-DO data bus. While DP7-DPO are outputs,
system logic can use the signals to check parity. While DP7-
DPO are inputs, the processor uses them to determine the state
of the PCHK output.
DP7-DPO are driven, sampled, and floated with the same tim-
ing as D63-DO. See the description for D63-DO on page 5-56.
DP7 corresponds to the high byte on the data bus (D63-D56)
and DPO corresponds to the low byte on the data bus (D7-DO).
To determine data parity, the bit values driven for each byte
on DP7-DPO are considered with the bit values driven for each
byte on D63-DO. For example, if the total number of 1 bits for
the byte on D63-D56 is even for DP7 and D63-D56, the address
is considered free of error (thus the term even parity). If the
number of 1 bits is odd, the byte is considered to have an error.
During single-transfer read cycles, parity is only checked for
enabled bytes as specified by BID-REO. During burst reads,
parity is checked for all eight bytes, regardless of BID-REO. If
a parity error is detected on a read, the processor asserts
PCHK.
Systems that do not implement data parity generation and
checking should tie DP7-DPO either High or Low and ignore
the PCHK output. In addition to generating and checking data
parity, the processor also generates and checks address parity
using the AP and APCHK signals. See page 5-32 and 5-33 for
details.
Bus Interface