AMD AMD5K86 - PEN (Parity Enable)

AMD~
AMD5~6 Processor Technical Reference Manual
18524B/O-Mar1996
5.2.40
Summary
Driven
Details
5-102
PCIIK (Parity Status)
output
The processor asserts PCHK during reads if it detects an even
parity error on one or more bytes of D63-DO during a read
cycle.
The processor drives PCHK for one clock, two clocks after each
BRDY during read cycles.
PCHK is driven for memory and I/O reads, locked reads, and
interrupt acknowledge operations in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, or
while PRDY is asserted. PCHK is not driven during any type of
write cycles or special bus cycles; or during the Shutdown,
Halt, Stop Grant, or Stop Clock states; or while HOFF, HLDA,
RESET, or INIT is asserted. While AHOLD is asserted, PCHK
is driven only to complete a bus cycle already begun before the
assertion of AHOLD.
To determine data parity, the bit value driven on DP7-DPO is
considered with the bit values driven on D63-DO. If the total
number of 1 bits is even for DP7-DPO and D63-DO, the byte is
considered free of error (thus the term even parity). If the num-
ber of 1 bits is odd, the byte is considered to have an error.
During burst reads, the processor checks all eight bytes of
D63-DO for errors, with respect to the even parity bit sampled
on DP7-DPO. During single-transfer reads, only the enable
bytes on D63-DO and the enabled parity bits on DP7-DPO (as
specified by BE7-BEU) are checked.
If PEN is asserted during the BRDY for a read cycle, and the
processor reports a data parity error on PCHK for that cycle,
the processor latches the physical address and cycle definition
of the failed bus cycle and (optionally) generates a machine
check exception. See the description of PEN on page 5-103 for
details.
If an error is reported on PCHK, the system must nevertheless
return all remaining BRDY s for that bus cycle-one BRDY for
single-transfer cycles and four BRDY s for burst cycles. Systems
that do not implement data parity generation and checking
should tie DP7-DPO either High or Low and ignore the PCHK
output.
Bus Interface