AMD AMD5K86 - TABLE 5-20. Bus-Cycle Order During Misaligned Transfers; Single-Transfer Misaligned Memory and I;O Transfers

18524B/O-Mar1996
I/O Read and Write
CLK
A31-A3
K
ADS
\
BrJ-llEO
K
IlRD'i'
o/C
/
063-00
M/fD
\
W(R
elK
AMDl'
AMD5J!J6 Processor Technical Reference Manual
Figure 5-4 shows an I/O read followed by an I/O write. The pro-
cessor accesses I/O when it executes an I/O instruction (any of
the INx or OUTx instructions). Accesses to memory-mapped
I/O ports appear on the bus as accesses to memory rather than
to the I/O address space.
The I/O-cycle protocol is nearly the same as the protocol for
read and write accesses to memory, shown in Figure 5-2, except
that MIIO = 0. Only data (not code) can be read or written from
the I/O address space. The cycle definition for an I/O code read
(D/C = 0, MIIO = 0, W!R = 0) defines an interrupt acknowledge
cycle, and the cycle-definition for an 110 code write (D/C = 0,
MIIO
= 0, W!R = 1) defines a special bus cycle.
The example in Figure 5-4 shows a single wait state separating
ADS and BRDY for the read. In actual systems, however, the
time will typically be longer.
I
I
X
I
I
/
\ /
\
/ /
(
I
H
I
: Read
I
I
Write
FIGURE 5-4.
I/O Read and Write
Bus Cycle Timing 5-147