AMD AMD5K86 - Bus Backoff (BOFF)

18524B/O-Mar1996
Bus Backoff (BOFF)
Bus Cycle Timing
AMD~
AMD5~6 Processor Technical Reference Manual
BUFF provides the fastest response of the three bus-hold
inputs. Unlike AHOLD and HOLD, BOW does not permit an
in-progress bus cycle to complete. It forces the processor off
the bus in the next clock, aborting any in-progress bus cycle
that the processor may have begun.
Figure 5-12 shows a burst read interrupted by BUFF. One clock
after sampling BUFF asserted, the processor aborts the entire
in-progress burst read and floats its bus. All output and bidi-
rectional signals used for memory or I/O accesses are floated.
The processor ignores all data and BRDY s returned by the sys-
tem during the aborted cycle. This is unlike BUFF on the 486
processor, which retains the data that had been transferred up
to the clock in which BUFF was asserted. BUFF has no effect
on writes to the processor's store buffer, except to delay them.
(The store buffer is situated between the execution units and
the data cache and is used for speculative stores, prior to being
written in non-speculative state to the data cache.)
Another bus master can begin driving cycles as early as two
clocks after BUFF is asserted. System logic or another bus mas-
ter may continue asserting BUFF for as long as it wants. The
processor has no way of breaking the hold. While the processor
is backed off, it continues to execute out of its instruction and
data caches, if possible. If it can no longer operate out of its
caches, it holds BREQ asserted continuously.
As early as one clock after BUFF is negated, the processor
restarts-from the beginning-any bus cycle that was aborted
when BUFF was asserted. This is unlike BUFF on the 486 pro-
cessor, which restarts only the transfers that did not complete
when BUFF was asserted. The processor may drive another
cycle with ADS as early as two clocks after any aborted cycle
completes. This allows one idle clock (also called a dead clock)
between any two bus cycles. If BUFF was asserted when ADS
was also asserted, however, ADS remains Low (floats asserted)
after BUFF is negated. In such a case, system logic must prop-
erly interpret the state of ADS when it negates BUFF.
Because of its ability to help resolve deadlock problems, BUFF
is required in virtually all systems with multiple caching mas-
ters. In such designs, system logic typically drives separate
BUFF signals to each bus master in the system. See Section
6.2.5 on page 6-14 for system configurations using BUFF.
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