AMD AMD5K86 - TCK (Test Clock)

18524B/0- Mar1996
Signal Descriptions
AMD~
AMD5,!J6 Processor Technical Reference Manual
processor is in the Stop Clock state, however, CLK must be
restarted before any other signals are changed.
STPcLK is the lowest-priority interrupt, as shown in Table 5-3
on page 5-17. R/S is the only interrupt or exception that is
acted upon while STPcLK is asserted, but R/S is only acted
upon in the Stop Grant state, not the Stop Clock state. Edge-
triggered interrupts (FLOSH, SlVII, INIT, NMI) are not latched
in the Stop Clock state; however, they are latched in the Stop
Grant state and are recognized after STPCLK is negated.
The AMD5
K
86 and Pentium processors differ in their support
for STPCLK in the following ways:
• In the Halt state, the AMD5
K
86 processor responds to STF-
eLK by entering the Stop Grant state. The Pentium proces-
sor ignores StPCLK in the Halt state.
• The Pentium processor guarantees that at least one instruc-
tion will be executed between the negation of STPcLK and
a subsequent reassertion of STPCLK. The AMD5
K
86 proces-
sor does not guarantee this.
• In the Halt or Stop Grant states, the AMD5
K
86 processor
cannot enter a low-power state if it does not have the bus
(that is, if AHOLD, BDFF or HLDA is asserted). The same
may not be true of the Pentium processor.
For further details on clock control and power management,
see Section 6.4 on page 6-33 and Section 6.6 on page 6-40.
5-127