AMD AMD5K86 - Page 245

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AMD5J!J6 Processor Technical Reference Manual 1 8524BjO-Mar1996
5-126
mal writeback (immediately if AHOLD is asserted, or delayed
if BUFF or HOLD are asserted) and returns to the state from
which it entered the Stop Grant Inquire state in the clock in
which it negates IIITM. If IIITM is not asserted, the processor
returns two clocks after EADS.
The processor enters the Stop Clock state when system logic
turns off CLK while STPCLK is asserted. This is the minimum-
power state and it can only be entered from the Stop Grant
state after BRDY has been returned for the Stop Grant special
bus cycle. In the Stop Clock state, the processor's phase-lock
loop and I/O buffers are disabled, except for the I/O buffers on
CLK and the Test Access Port (TAP) signals. System logic
should not change the state of any signals, and the processor
does not recognize any signal edges in the Stop Clock state.
When CLK is restarted, the processor returns to the Stop Grant
state, responds to inputs in the next clock, but cannot drive bus
cycles until its phase-lock loop is synchronized. The latter
takes several clocks (see the data sheet for this specification).
The CLK can be driven with a different frequency, and/or the
bus-to-processor clock ratio can be changed on the BF input
upon restarting CLK.
Thus, when CLK is restarted, the processor can:
• Respond to AHOLD, BUFF, or HOLD in the next clock after
CLK restarts, and
• Transition to the Stop Grant Inquire state as early as two
clocks after the assertion of AHOLD, two clocks after the
assertion of BUFF, or one clock after the assertion of HLDA
(if system logic drives an inquire cycle with EAIJS, INV and
an inquire address) and
• Drive IIITM and/or HIT two clocks after EADS.
However, if the inquire cycle hits a modified line, the processor
does not drive the writeback until several clocks after CLK
restarts (see the data sheet). In this case, the only indication
system logic receives of the write back is the ADS that initiates
it.
Thus, the processor recognizes AHOLD, BUFF, and HOLD dur-
ing the Stop Grant and Stop Grant Inquire states but not dur-
ing the Stop Clock state. When asserted in the Stop Grant
state, these signals cause the processor to restart its internal
clock and transition to the Stop Grant Inquire state. When the
Bus Interface